;
; FARL.SH Version 1.00 (C)1996 HUDSON SOFT
; HuC6273関連 アセンブラ用ヘッダーファイル(FARL.SH)
;
	ifndef _FARL_SH_
_FARL_SH_	equ	1

	ifndef __AURORA20
__AURORA20	equ	1
	endif

	include	farlfunc.sh

;************************************************************************
;*   Type definitions
;************************************************************************

	ifndef	NULL
NULL	equ	0
	endif

;************************************************************************
;*   Switch definitions
;************************************************************************
FARL_NOBLK	equ	1	; Do not block read/write
FARL_BLK	equ	2	; Block read/write

;************************************************************************
;*   Memory Map register definitions
;************************************************************************
;
; Memory Mapped Register Address Definition
;
FARL_CMD_FIFO			equ	$80500000	; Cmd FIFO
;				equ	$80500002	; Cmd FIFO
FARL_CMD_FIFO_STATUS		equ	$80500000	; Cmd FIFO Status
;				equ	$80500002	; Cmd FIFO Status
FARL_CMD_FIFO_CONTROL_REG	equ	$80500004	; Cmd FIFO Control Reg
FARL_CMT_BANK_SELECT_REG	equ	$80500006	; CMT Bank Select Reg.
FARL_CMT_START_ADDR_REG		equ	$80500008	; CMT Start Address Reg.
FARL_CMT_BYTE_COUNT_REG		equ	$8050000a	; CMT Byte Count Reg.
FARL_INTERRUPT_MASK_REG		equ	$8050000c	; Interrupt Mask Reg.
FARL_INTERRUPT_CLEAR_REG	equ	$8050000e	; Interrupt Clear Reg,
FARL_INTERRUPT_STATUS_REG	equ	$80500010	; Interrupt Status Reg
FARL_READBACK_REG		equ	$80500012	; ReaBack Reg.
FARL_H_TIMING_REG		equ	$80500014	; Horizontal Timing Reg
FARL_V_TIMING_REG		equ	$80500016	; Vertical Timing Reg.
FARL_SCT_ADDRESS_REG		equ	$80500018	; SCT Address Hi
FARL_SP_CONTROL_REG		equ	$8050001a	; Sprite Control Reg.
FARL_CD_RESULT_REG0		equ	$8050001c	; CD Result Reg. 0
FARL_CD_RESULT_REG1		equ	$8050001e	; CD Resutl Reg. 1
FARL_SP_WINDOW_CLIP_XLEFT	equ	$80500020	; SP window clip Xleft
FARL_SP_WINDOW_CLIP_YTOP	equ	$80500022	; SP window clip Ytop
FARL_SP_WINDOW_CLIP_XRIGHT	equ	$80500024	; SP window clip Xright
FARL_SP_WINDOW_CLIP_YBOTTOM	equ	$80500026	; SP window clip Ybottom
FARL_MISC_STATUS_REG		equ	$80500028	; Misc Status Reg.
FARL_ERROR_STATUS_REG		equ	$8050002a	; Error Status Reg.
FARL_DISPLAY_CONTROL_REG	equ	$8050002c	; Display Control Reg.
FARL_STATUS_CONTROL_REG		equ	$8050002e	; Status Control Reg.
FARL_CONFIG_REG			equ	$8050002e	; Config Reg.
FARL_TE_CODE_CONTROL_REG	equ	$80500030	; TE Code Control Reg
FARL_TE_CODE_ADDRESS_REG	equ	$80500032	; TE Address Control Reg
;				equ	$80500034	; Reserved
;				equ	$80500036	; Reserved
;				equ	$80500038	; Reserved
;				equ	$8050003a	; Reserved
FARL_RASTER_HIT_REG		equ	$8050003c	; Raster Hit Reg.
FARL_PE_TEST_REG		equ	$80500040	; PE Test Reg.
FARL_MEMORY_TEST_REG		equ	$80500042	; Memory Test Reg.
FARL_RESULT_REG0		equ	$80500060	; Result Reg[0]
FARL_RESULT_REG1		equ	$80500062	; Result Reg[1]
FARL_RESULT_REG2		equ	$80500064	; Result Reg[2]
FARL_RESULT_REG3		equ	$80500066	; Result Reg[3]
FARL_RESULT_REG4		equ	$80500068	; Result Reg[4]
FARL_RESULT_REG5		equ	$8050006a	; Result Reg[5]
FARL_RESULT_REG6		equ	$8050006c	; Result Reg[6]
FARL_RESULT_REG7		equ	$8050006e	; Result Reg[7]
FARL_RESULT_REG8		equ	$80500070	; Result Reg[8]
FARL_RESULT_REG9		equ	$80500072	; Result Reg[9]
FARL_RESULT_REG10		equ	$80500074	; Result Reg[10]
FARL_RESULT_REG11		equ	$80500076	; Result Reg[11]
FARL_RESULT_REG12		equ	$80500078	; Result Reg[12]
FARL_RESULT_REG13		equ	$8050007a	; Result Reg[13]
FARL_RESULT_REG14		equ	$8050007c	; Result Reg[14]
FARL_RESULT_REG15		equ	$8050007e	; Result Reg[15]

FARL_CMT_BUFFER			equ	$80510000	; CMT Buffer
FARL_TEXTURE_BUFFER		equ	$80510000	; Texture Buffer

;
; Config Register Bit Definition
;
FARL_CONFIG_TBW		equ	$0400	; Texuter Buffer width
FARL_CONFIG_TSZ_MASK	equ	$0300	; Texutre Buffer size mask
FARL_CONFIG_TSZ3	equ	$0300	; Texuter buffer size
FARL_CONFIG_TSZ2	equ	$0200	; Texuter buffer size
FARL_CONFIG_TSZ1	equ	$0100	; Texuter buffer size
FARL_CONFIG_TSZ0	equ	$0000	; Texuter buffer size
FARL_CONFIG_CREV_MASK	equ	$000f	; Chip Revision mask

;
; Interrupt Status/Mask/Clear Register Bit Definition
;
FARL_INTERRUPT_RHIT	equ	$8000	; Raster Hit
FARL_INTERRUPT_HBL	equ	$4000	; H Blank
FARL_INTERRUPT_VBL	equ	$2000	; V Blank
FARL_INTERRUPT_HSY	equ	$1000	; H Sync
FARL_INTERRUPT_VSY	equ	$0800	; V Sync
FARL_INTERRUPT_RBDONE	equ	$0400	; ReadBack done
FARL_INTERRUPT_TESYNC	equ	$0200	; TE Sync
FARL_INTERRUPT_SPDONE	equ	$0100	; Sprite done
FARL_INTERRUPT_CMDONE	equ	$0080	; Command Macro done
FARL_INTERRUPT_PESYNC	equ	$0040	; PE Sync
FARL_INTERRUPT_AEMP	equ	$0020	; Almost Empty
FARL_INTERRUPT_CSE	equ	$0010	; Command Sync error
FARL_INTERRUPT_AFL	equ	$0008	; Almost Full
FARL_INTERRUPT_OVF	equ	$0004	; Over flow
FARL_INTERRUPT_FSY	equ	$0002	; Frame sync
;			equ	$0001	; Not Defined

;
; Misc status Register Bit Definition
;
FARL_MISC_STATUS_SEL	equ	$8000	; VDP Select
FARL_MISC_STATUS_GSTD	equ	$4000	; Ghost Disable
FARL_MISC_STATUS_FGST	equ	$2000	; Force Ghost
FARL_MISC_STATUS_CMBSY	equ	$1000	; Commnad Macro Busy
FARL_MISC_STATUS_BCBSY	equ	$0800	; Buffer Clear Busy
FARL_MISC_STATUS_VBL	equ	$0400	; Vblank
FARL_MISC_STATUS_VSY	equ	$0200	; Vsync
FARL_MISC_STATUS_CMPND	equ	$0100	; Command Macro Pending
FARL_MISC_STATUS_RZBSY	equ	$0080	; RZ Busy
FARL_MISC_STATUS_MBSY	equ	$0040	; Memory Busy
FARL_MISC_STATUS_SBSY	equ	$0020	; Sprite Busy
FARL_MISC_STATUS_TEBSY	equ	$0010	; TE Busy
FARL_MISC_STATUS_PBSY	equ	$0008	; PE Busy
;			equ	$0004	; Not Defined
;			equ	$0002	; Not Defined
FARL_MISC_STATUS_NTRM	equ	$0001	; No Termination word

;
; Status Control Register Bit Definition
;
FARL_STATUS_CONTROL_HRST	equ 	$0002	; Hard reset
FARL_STATUS_CONTROL_SRST	equ	$0001	; Soft reset

;
; Display Control Register Bit Definition
;
FARL_DISPLAY_CONTROL_SVD11_MASK equ	$e000	; Select VD11 Mask
FARL_DISPLAY_CONTROL_VOD	equ	$1000	; Video out Disable
FARL_DISPLAY_CONTROL_DTT	equ	$0800	; Display to Texture Copy
FARL_DISPLAY_CONTROL_BCM_MASK	equ	$0600	; BCM Mask
FARL_DISPLAY_CONTROL_BCM3	equ	$0600	; Buffer Clear Mode
FARL_DISPLAY_CONTROL_BCM2	equ	$0400	; Buffer Clear Mode
FARL_DISPLAY_CONTROL_BCM1	equ	$0200	; Buffer Clear Mode
FARL_DISPLAY_CONTROL_BCM0	equ	$0000	; Buffer Clear Mode
FARL_DISPLAY_CONTROL_ASWP	equ	$0100	; Auto Swap Mode
FARL_DISPLAY_CONTROL_HCE	equ	$0080	; Hidden Clear Enable
FARL_DISPLAY_CONTROL_FSC_MASK	equ	$003f	; Frame Sync Count Mask

;
; Commnad FIFO Status Register
;
FARL_FIFO_STATUS_AFW_MASK	equ	$00ff	; Available FIFO word

;
; Horizontal Timing Regiseter
;
FARL_H_TIMING_SHB_MASK	equ	$ff80	; Start Hblank
FARL_H_TIMING_EHB_MASK	equ	$007f	; End Hblank

;
; Vertical Timing Register
;
FARL_V_TIMING_SVB_MASK	equ	$ff80	; Start Vblank
FARL_V_TIMING_EVB_MASK	equ	$007f	; End Vblank

;
; SCT Address Hi Register
;
FARL_SCT_SCTWDC_MASK	equ	$0700	; SCT word count
FARL_SCT_SBNK_MASK	equ	$00f8	; Sprite Bank Select
FARL_SCT_SCTNO_MASK	equ	$0007	; SCT number

;
; Sprite Controle Register
;
FARL_SPCONTRL_SCTOFSET_MASK	equ	$ff00 ; SCT offset
FARL_SPCONTRL_SCTWDC_MASK	equ	$00ff ; SCT word count

;
; A2.0
; CD Result Register
;
FARL_CDRST_MASK7	equ	$f000
FARL_CDRST_MASK6	equ	$0f00
FARL_CDRST_MASK5	equ	$00f0
FARL_CDRST_MASK4	equ	$000f
FARL_CDRST_MASK3	equ	$f000
FARL_CDRST_MASK2	equ	$0f00
FARL_CDRST_MASK1	equ	$00f0
FARL_CDRST_MASK0	equ	$000f

;
; CMT Bank Select Register
;
FARL_CBMK_MASK	equ	$001f		; Command bank select

;
; Error Status Register
;
FARL_ERR_SEC_MASK	equ	$0f00	; Sprite Error Code
FARL_ERR_PEST_MASK	equ	$00f0	; PE Status
FARL_ERR_TEST_MASK	equ	$000f	; TE Status

;
; TE Code Control Register
;
FARL_TE_CODE_FLPRF	equ	$0008	; TE Flip reg file
FARL_TE_CODE_TEMHLD	equ	$0001	; TE Hold

;************************************************************************
;*   TE register definitions
;************************************************************************
;
; 2.0
; Write TE Register with Address definition
;
FARL_OBJECT_MATRIX00_ADR	equ	2
FARL_OBJECT_MATRIX01_ADR	equ	4
FARL_OBJECT_MATRIX02_ADR	equ	12
FARL_OBJECT_MATRIX03_ADR	equ	14
FARL_OBJECT_MATRIX10_ADR	equ	16
FARL_OBJECT_MATRIX11_ADR	equ	20
FARL_OBJECT_MATRIX12_ADR	equ	22
FARL_OBJECT_MATRIX13_ADR	equ	30
FARL_OBJECT_MATRIX20_ADR	equ	32
FARL_OBJECT_MATRIX21_ADR	equ	34
FARL_OBJECT_MATRIX22_ADR	equ	38
FARL_OBJECT_MATRIX23_ADR	equ	40
FARL_OBJECT_MATRIX30_ADR	equ	48
FARL_OBJECT_MATRIX31_ADR	equ	50
FARL_OBJECT_MATRIX32_ADR	equ	52
FARL_OBJECT_MATRIX33_ADR	equ	54
FARL_NORMAL_MATRIX00_ADR	equ	56
FARL_NORMAL_MATRIX01_ADR	equ	58
FARL_NORMAL_MATRIX02_ADR	equ	60
FARL_NORMAL_MATRIX10_ADR	equ	62
FARL_NORMAL_MATRIX11_ADR	equ	64
FARL_NORMAL_MATRIX12_ADR	equ	66
FARL_NORMAL_MATRIX20_ADR	equ	68
FARL_NORMAL_MATRIX21_ADR	equ	70
FARL_NORMAL_MATRIX22_ADR	equ	72
FARL_SRC_MATRIX00_ADR		equ	97
FARL_SRC_MATRIX01_ADR		equ	99
FARL_SRC_MATRIX02_ADR		equ	101
FARL_SRC_MATRIX03_ADR		equ	103
FARL_SRC_MATRIX10_ADR		equ	105
FARL_SRC_MATRIX11_ADR		equ	107
FARL_SRC_MATRIX12_ADR		equ	109
FARL_SRC_MATRIX13_ADR		equ	111
FARL_SRC_MATRIX20_ADR		equ	113
FARL_SRC_MATRIX21_ADR		equ	115
FARL_SRC_MATRIX22_ADR		equ	117
FARL_SRC_MATRIX23_ADR		equ	119
FARL_SRC_MATRIX30_ADR		equ	121
FARL_SRC_MATRIX31_ADR		equ	123
FARL_SRC_MATRIX32_ADR		equ	125
FARL_SRC_MATRIX33_ADR		equ	127
FARL_LIGHT1_VECTOR0_ADR		equ	74
FARL_LIGHT1_VECTOR1_ADR		equ	76
FARL_LIGHT1_VECTOR2_ADR		equ	78
FARL_LIGHT2_VECTOR0_ADR		equ	80
FARL_LIGHT2_VECTOR1_ADR		equ	82
FARL_LIGHT2_VECTOR2_ADR		equ	84
FARL_AMBIENT_COE_ADR		equ	55
FARL_DIFFUSE_COE1_ADR		equ	57
FARL_DIFFUSE_COE2_ADR		equ	59
FARL_SPECULAR_COE1_ADR		equ	61
FARL_SPECULAR_COE2_ADR		equ	63
FARL_U_OFFSET_ADR		equ	86
FARL_V_OFFSET_ADR		equ	88
FARL_DEFAULT_COLOR_ADR		equ	90
FARL_WINDOW_CLIP_XLEFT_ADR	equ	65
FARL_WINDOW_CLIP_YTOP_ADR	equ	67
FARL_WINDOW_CLIP_XRIGHT_ADR	equ	69
FARL_WINDOW_CLIP_YBOTTOM_ADR	equ	71
FARL_WINDOW_SCALE_SCALEX_ADR	equ	75
FARL_WINDOW_SCALE_TRANSX_ADR	equ	77
FARL_WINDOW_SCALE_SCALEY_ADR	equ	79
FARL_WINDOW_SCALE_TRANSY_ADR	equ	81
FARL_MESH_PATTERN_ADR		equ	73
FARL_TE_CONTROL_ADR		equ	255

;
; Write TE Register Option Field
;
FARL_OBJECT_MATRIX		equ	$0
FARL_NORMAL_MATRIX		equ	$1
FARL_LIGHT0			equ	$2
FARL_LIGHT1			equ	$3
FARL_MATERIAL			equ	$4
FARL_EYE_VECTOR			equ	$5
FARL_TE_CONTROL_REG		equ	$6
FARL_TE_WIN_CLIP_REG		equ	$7
FARL_TE_SCALING_REG		equ	$8
FARL_TE_MESH_PATTERN_REG	equ	$9
FARL_TE_SET_SRC_MATRIX		equ	$a
FARL_TE_SET_VERTEX_REG		equ	$b
FARL_UV_OFFSET_REG		equ	$c
FARL_DEFAULT_COLOR_REG		equ	$d
FARL_TE_SET_REG			equ	$f

;
; TE Control Register Bit Definition
;
FARL_TE_RJM	equ	$0200	; Reject mode
FARL_TE_MSH	equ	$0100	; Mesh disable
FARL_TE_TTST0	equ	$0000	; TE test
FARL_TE_TTST1	equ	$0040	; TE test
FARL_TE_TTST2	equ	$0080	; TE test
FARL_TE_TTST3	equ	$00c0	; TE test
FARL_TE_LTEN	equ	$0020	; Light Enable
FARL_TE_SPEN	equ	$0010	; Specular Enable
;		equ	$0008	; Not defined
FARL_TE_BCE	equ	$0004	; Backface Cull Enable
FARL_TE_BDE	equ	$0002	; Backface Draw Enable
FARL_TE_NNF	equ	$0002	; Negative Normal Flip
FARL_TE_ICM	equ	$0001	; I-C Mode

;************************************************************************
;*   PE register definitions
;************************************************************************

;
; Write/Read PE Register Option Field
;
FARL_PE_TEXTURE_REG		equ	$0
FARL_PE_TARGET_REG		equ	$1
FARL_PE_MASK_REG		equ	$2
FARL_PE_CONTROL_REG		equ	$3
FARL_PE_CLEAR_Z_VALUE_REG	equ	$4
FARL_PE_FRAME_CONTROL_REG	equ	$5
FARL_PE_CLEAR_COLOR_VALUE_REG	equ	$6
FARL_PE_IC_MASK_REG		equ	$7
FARL_PE_FLASH_IC_VAL_REG	equ	$8
FARL_PE_CLEAR_TEXTURE_REG	equ	$9
FARL_PE_CLEAR_MASK_REG		equ	$a
FARL_PE_CWT_X_OFFSET_REG	equ	$b
FARL_PE_CWT_Y_OFFSET_REG	equ	$c

;
; PE Target Register Bit Definition
;
FARL_PE_WBEN_DZ		equ	$0006	; D/Z Buffer Write Enable
FARL_PE_WBEN_Z		equ	$0004	; Only Z Buffer Enable
FARL_PE_WBEN_D		equ	$0002	; Only D Buffer Enable
FARL_PE_WBEN_NONE	equ	$0000	; D/Z Write Disable
FARL_PE_RBSEL_Z		equ	$0001	; Read from Z Buffer
FARL_PE_RBSEL_D		equ	$0000	; Read from D Buffer

;
; PE Control Register Bit Definition
;
FARL_PE_SSFT	equ	$8000	; Shadow bit shift
FARL_PE_FWOZ	equ	$4000	; Fog Without Z
FARL_PE_RSDW	equ	$2000	; Reversed shadow
FARL_PE_SDW	equ	$1000	; Shadow Mode
FARL_PE_WDM	equ	$0800	; Wide Mode
FARL_PE_C12M	equ	$0400	; 12bit Mode
FARL_PE_ZCAT	equ	$0200	; Z Compare Always True
FARL_PE_OLEN	equ	$0100	; Overlay Enable
FARL_PE_PES	equ	$0080	; PE sync
FARL_PE_DZD	equ	$0040	; Dither Disable
FARL_PE_TLEN	equ	$0020	; Texture Light Enable
FARL_PE_TLM	equ	$0010	; Texture Light Mode
FARL_PE_FOG	equ	$0008	; Fog Mode
FARL_PE_RFOG	equ	$0004	; R-Fog Mode
FARL_PE_FLSH_I	equ	$0002	; Flash Intensity Mode
FARL_PE_FLSH_C	equ	$0001	; Flash Color Mode

;
; I-C Mask Definition
;
FARL_IC_MASK0	equ	$0fc7	; I=6, C=3
FARL_IC_MASK1	equ	$0f8f	; I=5, C=4
FARL_IC_MASK2	equ	$0f1f	; I=4, C=5
FARL_IC_MASK3	equ	$0e3f	; I=3, C=6
FARL_IC_MASK4	equ	$0fff	; 12 Bit Mode

;
; Another definition of IC_MASK
;
FARL_ICMASK_I6C3	equ	$0fc7	; I=6, C=3
FARL_ICMASK_I5C4	equ	$0f8f	; I=5, C=4
FARL_ICMASK_I4C5	equ	$0f1f	; I=4, C=5
FARL_ICMASK_I3C6	equ	$0e3f	; I=3, C=6
FARL_ICMASK_C12M	equ	$0fff	; 12 Bit Mode

;
; Frame Control Register Bit Definition
;
FARL_PE_SWV		equ	$0008	; Swap with V Blank
FARL_PE_SWP_BUFFER	equ	$0004	; Swap and switch buffer
FARL_PE_SWP_BUFFER0	equ	$0000	; Swap to Buffer 0
FARL_PE_SWP_BUFFER1	equ	$0002	; Swap to Buffer 1
FARL_PE_SWP		equ	$0001	; Swap

;
; PE Clear texture select register
;
FARL_PE_CLEAR_TEXTURE_ISFT0	equ	$0000	; Intensity Shift [1..0] = 00
FARL_PE_CLEAR_TEXTURE_ISFT1	equ	$0100	; Intensity Shift [1..0] = 01
FARL_PE_CLEAR_TEXTURE_ISFT2	equ	$0200	; Intensity Shift [1..0] = 10
FARL_PE_CLEAR_TEXTURE_ISFT3	equ	$0300	; Intensity Shift [1..0] = 11

;
; PE CWT X/Y Offset reg Bit Definition
;
FARL_PE_CWT_XWE		equ	$8000	; X wrap enable
FARL_PE_CWT_XBS0	equ	$0000	; X Bank size 4 bank
FARL_PE_CWT_XBS1	equ	$2000	; X Bank size 1 bank
FARL_PE_CWT_XBS2	equ	$4000	; X Bank size 2 bank

FARL_PE_CWT_YWE		equ	$8000	; Y wrap enable
FARL_PE_CWT_YBS0	equ	$0000	; Y Bank size 2 bank
FARL_PE_CWT_YBS1	equ	$2000	; Y Bank size 1 bank

FARL_PE_CWT_X_BANK4	equ	$0000	; X Bank size 4 bank
FARL_PE_CWT_X_BANK1	equ	$2000	; X Bank size 1 bank
FARL_PE_CWT_X_BANK2	equ	$4000	; X Bank size 2 bank
FARL_PE_CWT_Y_BANK2	equ	$0000	; Y Bank size 2 bank
FARL_PE_CWT_Y_BANK1	equ	$2000	; Y Bank size 1 bank

;************************************************************************
;*   System defintions
;************************************************************************

;
; Display definitions
;
FARL_SCREEN_WIDTH		equ	255
FARL_SCREEN_HIGHT		equ	255
FARL_WINDOW_WIDTH		equ	256
FARL_WINDOW_HEIGHT		equ	240
FARL_WIDDE_WINDOW_WIDTH		equ	320
FARL_WIDDE_WINDOW_HEIGHT	equ	200

;************************************************************************
;*   Defintions for primitives
;************************************************************************

;
; Data type definition for primtives 
;
FARL_SFT_FLOAT_VERTEX		equ	0
FARL_SFT_FLOAT_VNORM		equ	1
FARL_SFT_FLOAT_FNORM		equ	2
FARL_SFT_FLOAT_OBJECT_MATRIX	equ	3
FARL_SFT_FLOAT_NORMAL_MATRIX	equ	4
FARL_SFT_FLOAT_LIGHT		equ	5
FARL_SFT_FLOAT_EYEVECT		equ	6

FARL_SFT_FIX_VERTEX		equ	16
FARL_SFT_FIX_VNORM		equ	17
FARL_SFT_FIX_FNORM		equ	18
FARL_SFT_FIX_OBJECT_MATRIX	equ	19
FARL_SFT_FIX_NORMAL_MATRIX	equ	20
FARL_SFT_FIX_LIGHT		equ	21
FARL_SFT_FIX_EYEVECT		equ	22

FARL_FLOAT_VERTEX		equ	$0001
FARL_FLOAT_VNORM		equ	$0002
FARL_FLOAT_FNORM		equ	$0004
FARL_FLOAT_OBJECT_MATRIX	equ	$0008
FARL_FLOAT_NORMAL_MATRIX	equ	$0010
FARL_FLOAT_LIGHT		equ	$0020
FARL_FLOAT_EYEVECT		equ	$0040

FARL_FLOAT_ALL	equ	( FARL_FLOAT_VERTEX | FARL_FLOAT_VNORM | FARL_FLOAT_FNORM | FARL_FLOAT_OBJECT_MATRIX | FARL_FLOAT_NORMAL_MATRIX | FARL_FLOAT_LIGHT | FARL_FLOAT_EYEVECT )

FARL_FIX_VERTEX		equ	$010000
FARL_FIX_VNORM		equ	$020000
FARL_FIX_FNORM		equ	$040000
FARL_FIX_OBJECT_MATRIX	equ	$080000
FARL_FIX_NORMAL_MATRIX	equ	$100000
FARL_FIX_LIGHT		equ	$200000
FARL_FIX_EYEVECT	equ	$400000

FARL_FIX_ALL	equ	( FARL_FIX_VERTEX | FARL_FIX_VNORM | FARL_FIX_FNORM | FARL_FIX_OBJECT_MATRIX | FARL_FIX_NORMAL_MATRIX | FARL_FIX_LIGHT | FARL_FIX_EYEVECT )

	endif	; !_FARL_SH_
