/*  static char SccsId[] = "@(#)farl.h	1.15   2/16/96";
 *
 *         Copyright (c) KUBOTA Corporation and HUDSON SOFT,
 *                  1994, 1995 All Rights Reserved
 *
 *  This software comprises unpublished confidential information of
 *  KUBOTA Corp. and HUDSON SOFT. It may not be used, copied or made
 *  available to anyone, except in accordance with the license under
 *  which it is furnished.
 */

#ifndef _FARL_H_
#define _FARL_H_

#ifndef __AURORA20
#define __AURORA20
#endif

#include "farlfunc.h"

/************************************************************************
 *   Type definitions
 ************************************************************************/

#ifndef __UNSGN_TYPEDEFS__
#define	__UNSGN_TYPEDEFS__
typedef unsigned char u_char;
typedef unsigned short u_short;
typedef unsigned int u_int;
typedef unsigned long u_long;
#endif

#if !defined(NULL)
#define NULL 0
#endif

/************************************************************************
 *   Switch definitions
 ************************************************************************/
#define FARL_NOBLK	(1<<0)	/* Do not block read/write */
#define FARL_BLK	(1<<1)	/* Block read/write */

/************************************************************************
 *   Memory Map register definitions
 ************************************************************************/
/* 
 * Memory Mapped Register Address Definition
 */
#define FARL_CMD_FIFO		    0x80500000	/* Cmd FIFO		  */
/*				    0x80500002*//* Cmd FIFO		  */
#define FARL_CMD_FIFO_STATUS	    0x80500000	/* Cmd FIFO Status	  */
/*				    0x80500002*//* Cmd FIFO Status	  */
#define FARL_CMD_FIFO_CONTROL_REG   0x80500004	/* Cmd FIFO Control Reg	  */
#define FARL_CMT_BANK_SELECT_REG    0x80500006	/* CMT Bank Select Reg.	  */
#define FARL_CMT_START_ADDR_REG	    0x80500008	/* CMT Start Address Reg. */
#define FARL_CMT_BYTE_COUNT_REG	    0x8050000a	/* CMT Byte Count Reg.	  */
#define FARL_INTERRUPT_MASK_REG	    0x8050000c	/* Interrupt Mask Reg.	  */
#define FARL_INTERRUPT_CLEAR_REG    0x8050000e	/* Interrupt Clear Reg.	  */
#define FARL_INTERRUPT_STATUS_REG   0x80500010	/* Interrupt Status Reg.  */
#define FARL_READBACK_REG	    0x80500012	/* ReaBack Reg.		  */
#define FARL_H_TIMING_REG	    0x80500014	/* Horizontal Timing Reg  */
#define FARL_V_TIMING_REG	    0x80500016	/* Vertical Timing Reg.	  */
#define FARL_SCT_ADDRESS_REG	    0x80500018	/* SCT Address Hi	  */
#define FARL_SP_CONTROL_REG	    0x8050001a	/* Sprite Control Reg.	  */
#define FARL_CD_RESULT_REG0	    0x8050001c	/* CD Result Reg. 0	  */
#define FARL_CD_RESULT_REG1	    0x8050001e	/* CD Resutl Reg. 1	  */
#define FARL_SP_WINDOW_CLIP_XLEFT   0x80500020	/* SP window clip Xleft	  */
#define FARL_SP_WINDOW_CLIP_YTOP    0x80500022	/* SP window clip Ytop	  */
#define FARL_SP_WINDOW_CLIP_XRIGHT  0x80500024	/* SP window clip Xright  */
#define FARL_SP_WINDOW_CLIP_YBOTTOM 0x80500026	/* SP window clip Ybottom */
#define FARL_MISC_STATUS_REG	    0x80500028	/* Misc Status Reg.	  */
#define FARL_ERROR_STATUS_REG	    0x8050002a	/* Error Status Reg.	  */
#define FARL_DISPLAY_CONTROL_REG    0x8050002c	/* Display Control Reg.	  */
#define FARL_STATUS_CONTROL_REG	    0x8050002e	/* Status Control Reg.	  */
#define FARL_CONFIG_REG		    0x8050002e	/* Config Reg.		  */
#define FARL_TE_CODE_CONTROL_REG    0x80500030	/* TE Code Control Reg	  */
#define FARL_TE_CODE_ADDRESS_REG    0x80500032	/* TE Address Control Reg */
/*				    0x80500034*//* Reserved		  */
/*				    0x80500036*//* Reserved		  */
/*				    0x80500038*//* Reserved		  */
/*				    0x8050003a*//* Reserved		  */
#define FARL_RASTER_HIT_REG	    0x8050003c	/* Raster Hit Reg.	  */
#define FARL_PE_TEST_REG	    0x80500040	/* PE Test Reg.		  */
#define FARL_MEMORY_TEST_REG	    0x80500042	/* Memory Test Reg.	  */
#define FARL_RESULT_REG0	    0x80500060	/* Result Reg[0]	  */
#define FARL_RESULT_REG1	    0x80500062	/* Result Reg[1]	  */
#define FARL_RESULT_REG2	    0x80500064	/* Result Reg[2]	  */
#define FARL_RESULT_REG3	    0x80500066	/* Result Reg[3]	  */
#define FARL_RESULT_REG4	    0x80500068	/* Result Reg[4]	  */
#define FARL_RESULT_REG5	    0x8050006a	/* Result Reg[5]	  */
#define FARL_RESULT_REG6	    0x8050006c	/* Result Reg[6]	  */
#define FARL_RESULT_REG7	    0x8050006e	/* Result Reg[7]	  */
#define FARL_RESULT_REG8	    0x80500070	/* Result Reg[8]	  */
#define FARL_RESULT_REG9	    0x80500072	/* Result Reg[9]	  */
#define FARL_RESULT_REG10	    0x80500074	/* Result Reg[10]	  */
#define FARL_RESULT_REG11	    0x80500076	/* Result Reg[11]	  */
#define FARL_RESULT_REG12	    0x80500078	/* Result Reg[12]	  */
#define FARL_RESULT_REG13	    0x8050007a	/* Result Reg[13]	  */
#define FARL_RESULT_REG14	    0x8050007c	/* Result Reg[14]	  */
#define FARL_RESULT_REG15	    0x8050007e	/* Result Reg[15]	  */

#define FARL_CMT_BUFFER		    0x80510000	/* CMT Buffer 		  */
#define FARL_TEXTURE_BUFFER	    0x80510000	/* Texture Buffer 	  */

/* 
 * Config Register Bit Definition
 */
#define FARL_CONFIG_TBW		(1<<10)	/* Texuter Buffer width 	*/
#define FARL_CONFIG_TSZ_MASK	(3<<8)	/* Texutre Buffer size mask	*/
#define FARL_CONFIG_TSZ3	(3<<8)	/* Texuter buffer size   	*/
#define FARL_CONFIG_TSZ2	(2<<8)	/* Texuter buffer size   	*/
#define FARL_CONFIG_TSZ1	(1<<8)	/* Texuter buffer size   	*/
#define FARL_CONFIG_TSZ0	(0<<8)	/* Texuter buffer size   	*/
#define FARL_CONFIG_CREV_MASK	(0xf)	/* Chip Revision mask		*/

/*
 * Interrupt Status/Mask/Clear Register Bit Definition
 */
#define FARL_INTERRUPT_RHIT	(1<<15)	/* Raster Hit			*/
#define FARL_INTERRUPT_HBL	(1<<14)	/* H Blank			*/
#define FARL_INTERRUPT_VBL	(1<<13)	/* V Blank			*/
#define FARL_INTERRUPT_HSY	(1<<12)	/* H Sync			*/
#define FARL_INTERRUPT_VSY	(1<<11)	/* V Sync			*/
#define FARL_INTERRUPT_RBDONE	(1<<10)	/* ReadBack done		*/
#define FARL_INTERRUPT_TESYNC	(1<<9)	/* TE Sync			*/
#define FARL_INTERRUPT_SPDONE	(1<<8)	/* Sprite done			*/
#define FARL_INTERRUPT_CMDONE	(1<<7)	/* Command Macro done		*/
#define FARL_INTERRUPT_PESYNC	(1<<6)	/* PE Sync 			*/
#define FARL_INTERRUPT_AEMP	(1<<5)	/* Almost Empty			*/
#define FARL_INTERRUPT_CSE	(1<<4)	/* Command Sync error 		*/
#define FARL_INTERRUPT_AFL	(1<<3)	/* Almost Full 			*/
#define FARL_INTERRUPT_OVF	(1<<2)	/* Over flow	 		*/
#define FARL_INTERRUPT_FSY	(1<<1)	/* Frame sync 	 		*/
/*				(1<<0)*//* Not Defined			*/

/*
 * Misc status Register Bit Definition
 */
#define FARL_MISC_STATUS_SEL	(1<<15)	/* VDP Select			*/
#define FARL_MISC_STATUS_GSTD	(1<<14)	/* Ghost Disable		*/
#define FARL_MISC_STATUS_FGST	(1<<13)	/* Force Ghost			*/
#define FARL_MISC_STATUS_CMBSY	(1<<12)	/* Commnad Macro Busy		*/
#define FARL_MISC_STATUS_BCBSY	(1<<11)	/* Buffer Clear Busy		*/
#define FARL_MISC_STATUS_VBL	(1<<10)	/* Vblank			*/
#define FARL_MISC_STATUS_VSY	(1<<9)	/* Vsync			*/
#define FARL_MISC_STATUS_CMPND	(1<<8)	/* Command Macro Pending	*/
#define FARL_MISC_STATUS_RZBSY	(1<<7)	/* RZ Busy			*/
#define FARL_MISC_STATUS_MBSY	(1<<6)	/* Memory Busy			*/
#define FARL_MISC_STATUS_SBSY	(1<<5)	/* Sprite Busy			*/
#define FARL_MISC_STATUS_TEBSY	(1<<4)	/* TE Busy			*/
#define FARL_MISC_STATUS_PBSY	(1<<3)	/* PE Busy			*/
/*				(1<<2)*//* Not Defined			*/
/*				(1<<1)*//* Not Defined			*/
#define FARL_MISC_STATUS_NTRM	(1<<0)	/* No Termination word		*/

/*
 * Status Control Register Bit Definition
 */
#define FARL_STATUS_CONTROL_HRST (1<<1)	/* Hard reset			*/
#define FARL_STATUS_CONTROL_SRST (1<<0)	/* Soft reset			*/

/*
 * Display Control Register Bit Definition
 */
#define FARL_DISPLAY_CONTROL_SVD11_MASK (7<<13) /* Select VD11 Mask	*/
#define FARL_DISPLAY_CONTROL_VOD	(1<<12)	/* Video out Disable	*/
#define FARL_DISPLAY_CONTROL_DTT	(1<<11)	/* Display to Texture Copy */
#define FARL_DISPLAY_CONTROL_BCM_MASK	(3<<9)	/* BCM Mask		*/
#define FARL_DISPLAY_CONTROL_BCM3	(3<<9)	/* Buffer Clear Mode	*/
#define FARL_DISPLAY_CONTROL_BCM2	(2<<9)	/* Buffer Clear Mode	*/
#define FARL_DISPLAY_CONTROL_BCM1	(1<<9)	/* Buffer Clear Mode	*/
#define FARL_DISPLAY_CONTROL_BCM0	(0<<9)	/* Buffer Clear Mode	*/
#define FARL_DISPLAY_CONTROL_ASWP	(1<<8)	/* Auto Swap Mode	*/
#define FARL_DISPLAY_CONTROL_HCE	(1<<7)	/* Hidden Clear Enable	*/
#define FARL_DISPLAY_CONTROL_FSC_MASK	(0x3f)	/* Frame Sync Count Mask */

/*
 * Commnad FIFO Status Register
 */
#define FARL_FIFO_STATUS_AFW_MASK	(0xff)	/* Available FIFO word	*/

/*
 * Horizontal Timing Regiseter
 */
#define FARL_H_TIMING_SHB_MASK	(0xff80)	/* Start Hblank		*/
#define FARL_H_TIMING_EHB_MASK	(0x007f)	/* End Hblank		*/

/*
 * Vertical Timing Register
 */
#define FARL_V_TIMING_SVB_MASK	(0xff80)	/* Start Vblank		*/
#define FARL_V_TIMING_EVB_MASK	(0x007f)	/* End Vblank		*/

/*
 * SCT Address Hi Register
 */
#define FARL_SCT_SCTWDC_MASK	(0x700)	/* SCT word count		*/
#define FARL_SCT_SBNK_MASK	(0xf8)	/* Sprite Bank Select		*/
#define FARL_SCT_SCTNO_MASK	(0x7)	/* SCT number			*/

/*
 * Sprite Controle Register
 */
#define FARL_SPCONTRL_SCTOFSET_MASK	(0xff00) /* SCT offset		*/
#define FARL_SPCONTRL_SCTWDC_MASK	(0x00ff) /* SCT word count	*/

/* A2.0
 * CD Result Register
 */
#define FARL_CDRST_MASK7	0xf000
#define FARL_CDRST_MASK6	0x0f00
#define FARL_CDRST_MASK5	0x00f0
#define FARL_CDRST_MASK4	0x000f
#define FARL_CDRST_MASK3	0xf000
#define FARL_CDRST_MASK2	0x0f00
#define FARL_CDRST_MASK1	0x00f0
#define FARL_CDRST_MASK0	0x000f

/*
 * CMT Bank Select Register
 */
#define FARL_CBMK_MASK	(0x1f)		/* Command bank select 		*/

/*
 * Error Status Register
 */
#define FARL_ERR_SEC_MASK	(0x0f00)	/* Sprite Error Code	*/
#define FARL_ERR_PEST_MASK	(0x00f0)	/* PE Status		*/
#define FARL_ERR_TEST_MASK	(0x000f)	/* TE Status		*/

/*
 * TE Code Control Register
 */
#define FARL_TE_CODE_FLPRF	(1<<3)		/* TE Flip reg file	*/
#define FARL_TE_CODE_TEMHLD	(1<<0)		/* TE Hold		*/

/************************************************************************
 *   TE register definitions
 ************************************************************************/
/* 2.0
 * Write TE Register with Address definition
 */
#define FARL_OBJECT_MATRIX00_ADR	2
#define FARL_OBJECT_MATRIX01_ADR	4
#define FARL_OBJECT_MATRIX02_ADR	12
#define FARL_OBJECT_MATRIX03_ADR	14
#define FARL_OBJECT_MATRIX10_ADR	16
#define FARL_OBJECT_MATRIX11_ADR	20
#define FARL_OBJECT_MATRIX12_ADR	22
#define FARL_OBJECT_MATRIX13_ADR	30
#define FARL_OBJECT_MATRIX20_ADR	32
#define FARL_OBJECT_MATRIX21_ADR	34
#define FARL_OBJECT_MATRIX22_ADR	38
#define FARL_OBJECT_MATRIX23_ADR	40
#define FARL_OBJECT_MATRIX30_ADR	48
#define FARL_OBJECT_MATRIX31_ADR	50
#define FARL_OBJECT_MATRIX32_ADR	52
#define FARL_OBJECT_MATRIX33_ADR	54
#define FARL_NORMAL_MATRIX00_ADR	56
#define FARL_NORMAL_MATRIX01_ADR	58
#define FARL_NORMAL_MATRIX02_ADR	60
#define FARL_NORMAL_MATRIX10_ADR	62
#define FARL_NORMAL_MATRIX11_ADR	64
#define FARL_NORMAL_MATRIX12_ADR	66
#define FARL_NORMAL_MATRIX20_ADR	68
#define FARL_NORMAL_MATRIX21_ADR	70
#define FARL_NORMAL_MATRIX22_ADR	72
#define FARL_SRC_MATRIX00_ADR		97
#define FARL_SRC_MATRIX01_ADR		99
#define FARL_SRC_MATRIX02_ADR		101
#define FARL_SRC_MATRIX03_ADR		103
#define FARL_SRC_MATRIX10_ADR		105
#define FARL_SRC_MATRIX11_ADR		107
#define FARL_SRC_MATRIX12_ADR		109
#define FARL_SRC_MATRIX13_ADR		111
#define FARL_SRC_MATRIX20_ADR		113
#define FARL_SRC_MATRIX21_ADR		115
#define FARL_SRC_MATRIX22_ADR		117
#define FARL_SRC_MATRIX23_ADR		119
#define FARL_SRC_MATRIX30_ADR		121
#define FARL_SRC_MATRIX31_ADR		123
#define FARL_SRC_MATRIX32_ADR		125
#define FARL_SRC_MATRIX33_ADR		127
#define FARL_LIGHT1_VECTOR0_ADR		74
#define FARL_LIGHT1_VECTOR1_ADR		76
#define FARL_LIGHT1_VECTOR2_ADR		78
#define FARL_LIGHT2_VECTOR0_ADR		80
#define FARL_LIGHT2_VECTOR1_ADR		82
#define FARL_LIGHT2_VECTOR2_ADR		84
#define FARL_AMBIENT_COE_ADR		55
#define FARL_DIFFUSE_COE1_ADR		57
#define FARL_DIFFUSE_COE2_ADR		59
#define FARL_SPECULAR_COE1_ADR		61
#define FARL_SPECULAR_COE2_ADR		63
#define FARL_U_OFFSET_ADR		86
#define FARL_V_OFFSET_ADR		88
#define FARL_DEFAULT_COLOR_ADR		90
#define FARL_WINDOW_CLIP_XLEFT_ADR	65
#define FARL_WINDOW_CLIP_YTOP_ADR	67
#define FARL_WINDOW_CLIP_XRIGHT_ADR	69
#define FARL_WINDOW_CLIP_YBOTTOM_ADR	71
#define FARL_WINDOW_SCALE_SCALEX_ADR	75
#define FARL_WINDOW_SCALE_TRANSX_ADR	77
#define FARL_WINDOW_SCALE_SCALEY_ADR	79
#define FARL_WINDOW_SCALE_TRANSY_ADR	81
#define FARL_MESH_PATTERN_ADR		73
#define FARL_TE_CONTROL_ADR		255

/*
 * Write TE Register Option Field
 */
#define FARL_OBJECT_MATRIX		0x0
#define FARL_NORMAL_MATRIX		0x1
#define FARL_LIGHT0			0x2
#define FARL_LIGHT1			0x3
#define FARL_MATERIAL			0x4
#define FARL_EYE_VECTOR			0x5
#define FARL_TE_CONTROL_REG		0x6
#define FARL_TE_WIN_CLIP_REG		0x7
#define FARL_TE_SCALING_REG		0x8
#define FARL_TE_MESH_PATTERN_REG	0x9
#define FARL_TE_SET_SRC_MATRIX		0xa
#define FARL_TE_SET_VERTEX_REG		0xb
#define FARL_UV_OFFSET_REG		0xc
#define FARL_DEFAULT_COLOR_REG		0xd
#define FARL_TE_SET_REG			0xf

/*
 * TE Control Register Bit Definition
 */
#define FARL_TE_RJM		(1<<9)	/* Reject mode		*/
#define FARL_TE_MSH		(1<<8)	/* Mesh disable		*/
#define FARL_TE_TTST0		(0<<6)  /* TE test		*/
#define FARL_TE_TTST1		(1<<6)  /* TE test		*/
#define FARL_TE_TTST2		(2<<6)  /* TE test		*/
#define FARL_TE_TTST3		(3<<6)  /* TE test		*/
#define FARL_TE_LTEN		(1<<5)	/* Light Enable		*/
#define FARL_TE_SPEN		(1<<4)	/* Specular Enable	*/
/*				(1<<3)*//* Not defined		*/
#define FARL_TE_BCE		(1<<2)	/* Backface Cull Enable */
#define FARL_TE_BDE		(1<<1)	/* Backface Draw Enable */
#define FARL_TE_NNF		(1<<1)	/* Negative Normal Flip */
#define FARL_TE_ICM		(1<<0)	/* I-C Mode 		*/

/************************************************************************
 *   PE register definitions
 ************************************************************************/
/*
 * Write/Read PE Register Option Field
 */
#define FARL_PE_TEXTURE_REG		0x0
#define FARL_PE_TARGET_REG		0x1
#define FARL_PE_MASK_REG		0x2
#define FARL_PE_CONTROL_REG		0x3
#define FARL_PE_CLEAR_Z_VALUE_REG	0x4
#define FARL_PE_FRAME_CONTROL_REG	0x5
#define FARL_PE_CLEAR_COLOR_VALUE_REG	0x6
#define FARL_PE_IC_MASK_REG		0x7
#define FARL_PE_FLASH_IC_VAL_REG	0x8
#define FARL_PE_CLEAR_TEXTURE_REG	0x9
#define FARL_PE_CLEAR_MASK_REG		0xa
#define FARL_PE_CWT_X_OFFSET_REG	0xb
#define FARL_PE_CWT_Y_OFFSET_REG	0xc

/*
 * PE Target Register Bit Definition
 */
#define FARL_PE_WBEN_DZ		(3<<1)   /* D/Z Buffer Write Enable */
#define FARL_PE_WBEN_Z		(2<<1)   /* Only Z Buffer Enable */
#define FARL_PE_WBEN_D		(1<<1)   /* Only D Buffer Enable */
#define FARL_PE_WBEN_NONE	(0<<1)   /* D/Z Write Disable */
#define FARL_PE_RBSEL_Z		(1<<0)   /* Read from Z Buffer */
#define FARL_PE_RBSEL_D		(0<<0)   /* Read from D Buffer */

/*
 * PE Control Register Bit Definition
 */
#define FARL_PE_SSFT		(1<<15)	/* Shadow bit shift		*/
#define FARL_PE_FWOZ		(1<<14)	/* Fog Without Z		*/
#define FARL_PE_RSDW		(1<<13)	/* Reversed shadow		*/
#define FARL_PE_SDW		(1<<12)	/* Shadow Mode			*/
#define FARL_PE_WDM		(1<<11)	/* Wide Mode			*/
#define FARL_PE_C12M		(1<<10) /* 12bit Mode			*/
#define FARL_PE_ZCAT		(1<<9)	/* Z Compare Always True	*/
#define FARL_PE_OLEN		(1<<8)	/* Overlay Enable		*/
#define FARL_PE_PES		(1<<7)	/* PE sync			*/
#define FARL_PE_DZD		(1<<6)	/* Dither Disable		*/
#define FARL_PE_TLEN		(1<<5)	/* Texture Light Enable		*/
#define FARL_PE_TLM		(1<<4)	/* Texture Light Mode		*/
#define FARL_PE_FOG		(1<<3)	/* Fog Mode			*/
#define FARL_PE_RFOG		(1<<2)	/* R-Fog Mode			*/
#define FARL_PE_FLSH_I		(1<<1)	/* Flash Intensity Mode		*/
#define FARL_PE_FLSH_C		(1<<0)	/* Flash Color Mode		*/

/*
 * I-C Mask Definition
 */
#define FARL_IC_MASK0		0xFC7	/* I=6, C=3    */
#define FARL_IC_MASK1		0xF8F	/* I=5, C=4    */
#define FARL_IC_MASK2		0xF1F	/* I=4, C=5    */
#define FARL_IC_MASK3		0xE3F	/* I=3, C=6    */
#define FARL_IC_MASK4		0xFFF	/* 12 Bit Mode */

/*
 * Another definition of IC_MASK
 */
#define FARL_ICMASK_I6C3	0xFC7	/* I=6, C=3    */
#define FARL_ICMASK_I5C4	0xF8F	/* I=5, C=4    */
#define FARL_ICMASK_I4C5	0xF1F	/* I=4, C=5    */
#define FARL_ICMASK_I3C6	0xE3F	/* I=3, C=6    */
#define FARL_ICMASK_C12M	0xFFF	/* 12 Bit Mode */

/*
 * Frame Control Register Bit Definition
 */
#define FARL_PE_SWV		(1<<3)  /* Swap with V Blank */
#define FARL_PE_SWP_BUFFER	(2<<1)  /* Swap and switch buffer */
#define FARL_PE_SWP_BUFFER0	(0<<1)  /* Swap to Buffer 0 */
#define FARL_PE_SWP_BUFFER1	(1<<1)  /* Swap to Buffer 1 */
#define FARL_PE_SWP		(1<<0)  /* Swap */

/*
 * PE Clear texture select register
 */
#define FARL_PE_CLEAR_TEXTURE_ISFT0  (0<<8)  /* Intensity Shift [1..0] = 00 */
#define FARL_PE_CLEAR_TEXTURE_ISFT1  (1<<8)  /* Intensity Shift [1..0] = 01 */
#define FARL_PE_CLEAR_TEXTURE_ISFT2  (2<<8)  /* Intensity Shift [1..0] = 10 */
#define FARL_PE_CLEAR_TEXTURE_ISFT3  (3<<8)  /* Intensity Shift [1..0] = 11 */

/*
 * PE CWT X/Y Offset reg Bit Definition
 */
#define FARL_PE_CWT_XWE		(1<<15)	/* X wrap enable */
#define FARL_PE_CWT_XBS0	(0<<13) /* X Bank size 4 bank */
#define FARL_PE_CWT_XBS1	(1<<13) /* X Bank size 1 bank */
#define FARL_PE_CWT_XBS2	(2<<13) /* X Bank size 2 bank */

#define FARL_PE_CWT_YWE		(1<<15)	/* Y wrap enable */
#define FARL_PE_CWT_YBS0	(0<<13) /* Y Bank size 2 bank */
#define FARL_PE_CWT_YBS1	(1<<13) /* Y Bank size 1 bank */

#define FARL_PE_CWT_X_BANK4	(0<<13) /* X Bank size 4 bank */
#define FARL_PE_CWT_X_BANK1	(1<<13) /* X Bank size 1 bank */
#define FARL_PE_CWT_X_BANK2	(2<<13) /* X Bank size 2 bank */
#define FARL_PE_CWT_Y_BANK2	(0<<13) /* Y Bank size 2 bank */
#define FARL_PE_CWT_Y_BANK1	(1<<13) /* Y Bank size 1 bank */

/************************************************************************
 *   System defintions
 ************************************************************************/
/*
 * Display definitions
 */
#define FARL_SCREEN_WIDTH		(256-1)
#define FARL_SCREEN_HIGHT		(256-1)
#define FARL_WINDOW_WIDTH		(256)
#define FARL_WINDOW_HEIGHT		(240)
#define FARL_WIDDE_WINDOW_WIDTH		(320)
#define FARL_WIDDE_WINDOW_HEIGHT	(200)

/************************************************************************
 *   Defintions for primitives
 ************************************************************************/
/*
 * Data type definition for primtives 
 */
#define FARL_SFT_FLOAT_VERTEX		0
#define FARL_SFT_FLOAT_VNORM		1
#define FARL_SFT_FLOAT_FNORM		2
#define FARL_SFT_FLOAT_OBJECT_MATRIX	3
#define FARL_SFT_FLOAT_NORMAL_MATRIX	4
#define FARL_SFT_FLOAT_LIGHT		5
#define FARL_SFT_FLOAT_EYEVECT		6

#define FARL_SFT_FIX_VERTEX		16
#define FARL_SFT_FIX_VNORM		17
#define FARL_SFT_FIX_FNORM		18
#define FARL_SFT_FIX_OBJECT_MATRIX	19
#define FARL_SFT_FIX_NORMAL_MATRIX	20
#define FARL_SFT_FIX_LIGHT		21
#define FARL_SFT_FIX_EYEVECT		22

#define FARL_FLOAT_VERTEX		(1<<FARL_SFT_FLOAT_VERTEX)
#define FARL_FLOAT_VNORM		(1<<FARL_SFT_FLOAT_VNORM)
#define FARL_FLOAT_FNORM		(1<<FARL_SFT_FLOAT_FNORM)
#define FARL_FLOAT_OBJECT_MATRIX	(1<<FARL_SFT_FLOAT_OBJECT_MATRIX)
#define FARL_FLOAT_NORMAL_MATRIX	(1<<FARL_SFT_FLOAT_NORMAL_MATRIX)
#define FARL_FLOAT_LIGHT		(1<<FARL_SFT_FLOAT_LIGHT)
#define FARL_FLOAT_EYEVECT		(1<<FARL_SFT_FLOAT_EYEVECT)

#define FARL_FLOAT_ALL			( FARL_FLOAT_VERTEX | \
					FARL_FLOAT_VNORM | \
					FARL_FLOAT_FNORM | \
					FARL_FLOAT_OBJECT_MATRIX | \
					FARL_FLOAT_NORMAL_MATRIX | \
					FARL_FLOAT_LIGHT | \
					FARL_FLOAT_EYEVECT)

#define FARL_FIX_VERTEX			(1<<FARL_SFT_FIX_VERTEX)
#define FARL_FIX_VNORM			(1<<FARL_SFT_FIX_VNORM)
#define FARL_FIX_FNORM			(1<<FARL_SFT_FIX_FNORM)
#define FARL_FIX_OBJECT_MATRIX		(1<<FARL_SFT_FIX_OBJECT_MATRIX)
#define FARL_FIX_NORMAL_MATRIX		(1<<FARL_SFT_FIX_NORMAL_MATRIX)
#define FARL_FIX_LIGHT			(1<<FARL_SFT_FIX_LIGHT)
#define FARL_FIX_EYEVECT		(1<<FARL_SFT_FIX_EYEVECT)

#define FARL_FIX_ALL			( FARL_FIX_VERTEX | FARL_FIX_VNORM | \
					FARL_FIX_FNORM | \
					FARL_FIX_OBJECT_MATRIX | \
					FARL_FIX_NORMAL_MATRIX | \
					FARL_FIX_LIGHT | \
					FARL_FIX_EYEVECT)
#endif	/* _FARL_H_ */
